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 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16721
3.3V 20-Bit Flip-Flop with 3-STATE Outputs
Product Features
* * * * * * * * PI74ALVCH16721 is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25C Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors Industrial operation at 40C to +85C Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are produced in the Companys advanced 0.5 micron CMOS technology, achieving industry leading speed. The PI74ALVCH16721 is a 20-bit flip-flop with 3-state outputs designed specifically for 2.3V to 3.6V VCC operation. The PI74ALVCH16721 is designed with edge-triggered D-type flipflops with qualified clock storage. On the positive transition of clock (CLK) input, the device provides true data at the Q outputs, provided that the clock-enable (CLKEN) input is LOW. If CLKEN is HIGH, no data is stored. A buffered output-enable (OE) input can be used to place the 20 outputs in either a normal logic state (HIGH or LOW level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capacity to drive bus lines without the need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The PI74ALVCH16721 data has Bus Hold which retains the data inputs last state whenever the data input goes to highimpedance preventing floating inputs and eliminating the need for pullup/down resistors.
Logic Block Diagram
1 56 29 2 55
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Product Pin Description
Pin Name OE CLKEN CLK Dx Qx GND VCC Description Output Enable Input (Active LOW) Clock Enable Input (Active LOW) Clock Input (Active HIGH) Data Inputs 3-State Outputs Ground Power
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16721 3.3V 20-Bit Flip-Flop with 3-State Outputs
Truth Table(1)
Inputs OE L L L L H CLKEN H L L L X CLK X L or H X Dx X H L X X Outputs Qx Q0 H L Q0 Z
Product Pin Configuration
OE Q1 Q2 GND Q3 Q4 VCC Q5 Q6 Q7 GND Q8 Q9 Q10 Q11 Q12 Q13 GND Q14 Q15 Q16 VCC Q17 Q18 GND Q19 Q20 NC
Notes: 1. H = High Signal Level L = Low Signal Level X = Don't Care or Irrelevant Z = High Impedance = LOW-to-HIGH Transition
56 55 54 53 52 51 50 49 48 47 46 45
CLK D1 D2 GND D3 D4 VCC D5 D6 D7 GND D8 D9 D10 D11 D12 D13 GND D14 D15 D16 VCC D17 D18 GND D19 D20 CLKEN
1 2 3 4 5 6 7 8 9 10 11 12 13
44 14 43 56-Pin 15 A,V 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 25 26 27 28 33 32 31 30 29
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16721 3.3V 20-Bit Flip-Flop with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........................................................... 65C to +150C Ambient Temperature with Power Applied ........................ 40C to +85C Input Voltage Range, VIN ...................................................... 0.5V to VCC +0.5V Output Voltage Range, VOUT ............................................... 0.5V to VCC +0.5V DC Input Voltage .................................................................... 0.5V to +5.0V DC Output Current ............................................................................ 100 mA Power Dissipation .................................................................................. 1.0W
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = 40C to +85C, VCC = 3.3V 10%)
Parame te rs VCC VIH(3) VIL(3) VIN(3) VOUT(3) D e s cription Supply Voltage Input HIGH Voltage VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V 0 0 IOH = - 100A, VCC = Min. to Max. O utput HIGH Voltage VIH = 1.7V, IOH = - 6mA, VCC = 2.3V VIH = 1.7V, IOH = - 12mA, VCC = 2.3V VIH = 2.0V, IOH = - 12mA, VCC = 2.7V VIH = 2.0V, IOH = - 12mA, VCC = 3.0V VIH = 2.0V, IOH = - 24mA, VCC = 3.0V IOL = 100A, VIL = Min. to Max. VOL O utput LO W Voltage VIL = 0.7V, IOL = 6mA, VCC = 2.3V VIL = 0.7V, IOL = 12mA, VCC = 2.3V VIL = 0.8V, IOL = 12mA, VCC = 2.7V VIL = 0.8V, IOL = 24mA, VCC = 3.0V O utput HIGH Current VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 2.3V VCC = 2.7V VCC = 3.0V
3
Te s t Conditions (1)
M in. 2.3 1.7 2.0
Typ.(2)
M ax. 3.6
Units
Input LO W Voltage Input Voltage O utput Voltage
0.7 0.8 VCC VCC
VCC - 0.2 2.0 1.7 2.2 2.4 2.0 0.2 0.4 0.7 0.4 0.55 - 12 - 12 - 24 12 12 24
PS8090C 02/07/00
V
VOH
IOH(3)
mA
IOL(3)
O utput LO W Current
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16721 3.3V 20-Bit Flip-Flop with 3-State Outputs
DC Electrical Characteristics-Continued (Over the Operating Range, TA = 40C to +85C, VCC = 3.3V 10%)
Parame te rs De s cription IIN Input Current Te s t Conditions (1) VIN = VCC or GND, VCC = 3.6V VIN = 0.7V, VCC = 2.3V IIN (HOLD) Input Hold Current VIN = 1.7V, VCC = 2.3V VIN = 0.8V, VCC = 3.0V VIN = 2.0V, VCC = 3.0V VIN = 0 to 3.6V, VCC = 3.6V IOZ ICC ICC Output Current (3- STATE Outputs) Supply Current Supply Current per Input @ TTL HIGH Control Inputs Data Inputs Outputs VOUT = VCC or GND, VCC = 3.6V VCC = 3.6V, IOUT = 0A, VIN = GND or VCC VCC = 3.0V to 3.6V One Input at VCC - 0.6V Other Inputs at VCC or GND VIN = VCC or GND, VCC = 3.3V VO = VCC or GND, VCC = 3.3V 3 6 7 pF 45 - 45 75 - 75 500 10 40 750 A M in. Typ.(2) M ax. 5 Units
CI CO
Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient and maximum loading. 3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating.
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16721 3.3V 20-Bit Flip-Flop with 3-State Outputs
Switching Characteristics over Operating Range(1)
Parame te rs fCLOCK fMAX tPLH, tPHL tPZH, tPZL tPHX tSU tSU tH tH tW t/v(4) De s cription Clock Frequency Maximum Frequency Propogation Delay CLK to Qx Output Enable Time OE to Qx Output Disable Time OE to Qx Data Before CLK CLKEN Before CLK Data After CLK CLKEN After CLK CLK HIGH or LOW Input Transition RISE or FALL Pulse Width(3) CL = 50pF RL = 500 4 3.4 0 0 3.3 0 10 1.0 Conditions (1) VCC = 2.5V 0.2V M in.(2) 0 150 5.6 6.1 5.5 3.6 3.1 0 0 3.3 0 10 1.0 M ax. 150 VCC = 2.7V M in.(2) 0 150 5.1 5.8 4.7 3.1 2.7 0 0 3.3 0 10 ns/V 1.0 M ax. 150 VCC = 3.3V 0.3V M in.(2) 0 150 4.3 4.8 4.4 M ax. 150 Units
MHz
ns
Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Recommended operating condition.
Operating Characteristics, TA = 25C
Parame te r CPD Power Dissipation Capacitance Outputs Enabled Outputs Disabled Te s t Conditions VCC = 2.5V 0.2V Typ. 55 46 59 49 VCC = 3.3V 0.3V Units
CL = 50pF, f = 10 MHz
pF
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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PS8090C 02/07/00


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